1. Field of the Invention
The present invention relates generally to systems for integrated circuit manufacture. More particularly, the present invention relates to a system and method for automating the photolithography procedure utilized in fabricating integrated circuits and for automating the manufacture of integrated circuits having an optimal feature size.
2. Description of the Related Art
The manufacture of integrated circuits is a complex process which combines the technologies of photolithography, physics and chemistry. In one common method of semiconductor manufacture, wafers of pure silicon are coated with thin layers of photo-resist. Each coated wafer is then exposed to a light source which is projected through an etched mask layer imaged adjacent to the wafer. The etched mask layer only passes light to selected regions of the wafers, resulting in the exposing of the resist at those selected regions. The exposed regions of the photo-resist are removed, opening small windows of silicon on the surface of the wafer. These windows enable doping impurities to be diffused or deposited onto the exposed wafer regions. Following exposure of the windowed regions of the wafer to the doping impurities, the resist is completely removed from the wafer and the process is repeated using additional layers of mask levels. Additional photo-resist layers may be subsequently used to selectively mask the wafer surface for further processing such as etching, formation of interconnect lines, and the like. Using this lithographic-diffusion technique, very complex systems of electronically active devices can be accurately produced. From start to finish it is not unusual for six to twenty mask levels to be used in the wafer manufacturing process.
Important advantages are achieved with semiconductor devices by making the individual electronic device features as small as possible. The smaller the individual devices are, the more devices that can be put on a single IC wafer. Higher densities, therefore, translate into lower materials cost for individual components. A further significant benefit of this reduced materials cost results from the fact that discrete defects on the silicon substrate randomly exist across the wafer. When the individual circuit dice consume smaller areas of substrate, the probability of silicon defects per unit die is decreased, thus resulting in higher yields and lower per unit cost. In addition to savings in manufacturing costs achievable with reduced device sizes, device speeds are increased and power is reduced per unit device as the devices become smaller.
Thus, what is needed, and one problem which is addressed by the present invention, is to design circuits having the smallest possible device feature sizes for an available manufacturing process.
A second problem that is being faced in the electronics industry, is the need for increasingly faster design and production cycles for semiconductor devices. The economies of integration, which can be achieved by utilizing customized semiconductor devices in electronic systems, makes it highly desirable to design application specific circuits where possible. One limitation to using customized circuits in electronic products is that the amount of time required to design and produce these integrated circuits makes them impractical for many commercial applications. Often, producers of electronic goods will design a product using conventional discrete or off-the-shelf components, and then over time begin to integrate and customize the circuitry as revisions to the product are produced. There may be a time in the not-too-distant future when a system will enable the circuit designer to enter a schematic of a required electronic device, and have a tabletop unit sitting next to the computer begin immediately generating finished integrated circuit products, much in the same way a printer reproduces a paper document. Today, however, the complexities of the device physics and chemistry require the use of complex lithography systems and highly controlled chemical process ovens.
What is further needed, therefore, is a system and method for to automating photolithography procedures used in the fabrication of integrated circuits.
In accordance with the present invention, a system enables the automated photolithography of semiconductor integrated circuits. The system is controlled as a processor which is coupled to a Rayleigh derator, a form factor generator, a logic synthesizer, a lithography module and a wafer process. A Rayleigh processor receives light source and numerical aperture information from the lithography module, and also receives manufacturing process data from the wafer process. The light source information, the numerical aperture data and the manufacturing information are combined together to derate the theoretical minimum resolvable feature size which may be manufactured using a wafer process. This derating consists of a combined consideration of both theoretical limitations produced by the lithography equipment, as well as measured results from manufacturing variations occurring in the wafer process. The Rayleigh processor communicates this minimum resolvable feature size to the form factor processor, which then uses standard sizing models to determine the minimum device size for each transistor in a circuit design net list. The form factor processor receives IDS (drain source current), VGS (gate to source voltage), and gate length information from the circuit net list and calculates a corresponding minimum manufacturable gate width which can be used to satisfy the design requirements. Once all transistors in the net list have been sized, a logic processor produces a physical design for production of a photolithographic wafer mask set. Following production of the wafer mask set, wafers are then manufactured in the wafer process. Manufacturing and yield data from the processed wafers is then collected and used to subsequently update the Rayleigh processor. In this way, the present invention is achieved: a direct coupling between the measurement of wafer process parameters and the automated sizing of semiconductor devices. Such invention enables the production of circuits having the smallest manufacturable device sizes available for the given photolithography equipment and wafer process.
Although the preferred embodiment relies on a single computer to control the automated system of the present invention, an alternative embodiment utilizes multiple computers or processing facilities to control various aspects of the system. For instance, in one alternative embodiment, Rayleigh derating is controlled using a first computer with the minimum feature size being stored. The minimum feature size is then conventionally communicated to a second computer which controls form factor generation and layout generation. A third computer controls the etching of wafer masks. A fourth computer monitors the wafer process and collects test results data for communication back to the Rayleigh derating performed by the first computer.